The present invention relates to the field of time dependency maintenance in serial and parallel operations of an electronic system. More particularly, the present invention relates to a system and method for efficient utilization of electronic hardware in conversions that includes parallel operations.
Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Digital computers, calculators, audio devices, video equipment, telephone systems and a number of other electronic systems and circuits have facilitated increased productivity and reduced costs in a variety of activities, including the analysis and communication of data, ideas and trends in most areas of business, science, education and entertainment. These electronic systems and circuits are usually arranged in a variety of complicated configurations governed by processing and communication limitations, including time dependencies and ordering constraints. For example, some systems rely on sequential processing or communications (e.g., first in first out (FIFO)) and some systems rely on parallel processing or communications. Sequential processing and communication systems are typically cheaper and easier to design and build than parallel processing and communication systems. Parallel processing and communication systems are usually faster than sequential processing and communication systems. Electronic system design decisions are affected by these and other comparative attributes of different processing and communication architectures.
For most electrical systems to operate properly it is usually critical to maintain timing dependencies and follow ordering constraints. For example, in a parallel process or communication system it is usually important for information associated with a particular period in time be forwarded to certain key points at the same time. If the information is not forwarded together at the appropriate time a parallel process will not remain xe2x80x9cparallelxe2x80x9d and will not operate correctly. In sequential processing and communication systems information is usually divided into units that are transmitted or processed one piece at a time with one piece of information following another. In some situations it is critical for one piece of information to follow another particular piece of information and if the appropriate order is not maintained the system will not operate properly.
Computer systems are an example of electronic systems that often rely on sequential or parallel processing and communications. A partial list of areas impacted by these applications include the generation of special effects for movies, realistic computer-generated three-dimensional graphic images and animation, real-time simulations, video teleconferencing, Internet-related applications, computer games, telecommuting, virtual reality, high-speed databases, real-time interactive simulations, medical diagnostic imaging, word processing, spread sheets etc. FIG. 1 shows a schematic of a typical prior art computer graphics system 100. Computer graphics system 100 comprises a central processing unit (CPU) 101, a main memory 102, graphics system 103, mass storage device 105, keyboard controller 106, keyboard 108, printer 109 and display monitor 110, all of which are coupled to bus 107. CPU 101 handles most of the control and data processing. In one embodiment CPU 101 operates in a sequential manner and in another embodiment CPU 101 comprises multiple processing components that operate in parallel. Main memory 102 provides a convenient method of storing data for quick retrieval by CPU 101. Graphics system 103 processes image data in pipelined stages including pixel information. Mass storage device 105 stores data associated with multiple images and applications. Keyboard controller 106 controls keyboard 108, which operates as an input device. Printer 109 prints hard copies of graphical images and display monitor 110 displays graphical images.
Computer systems typically have some method of interfacing with users. Often, this interfacing involves the graphical representation of images (graphics) on a display screen, other visualization device or a hard copy printout. Typically, these images are generated by computer graphics systems that simulate and display images of real or abstract objects. In most computer graphic systems an image is represented as a raster (an array) of logical picture elements (pixels). A pixel is usually a rectangle, but can be other shapes. The computer graphics system utilizes a rasterization process to assign parameter values to each pixel. These parameter values are digital values corresponding to certain attributes of the image (e.g. color, depth, etc.) measured over a small area of the image represented by a pixel. Typically each graphical image is represented by thousands of combined pixels.
In a complex or three dimensional (3D) computer generated graphical image, objects are typically described by graphics data models that define the shape of the object, the object""s attributes, and where the object is positioned. As details become finer and more intricate it is often advantageous to map an image onto a surface. Mapping an image onto a surface is usually accomplished through texture mapping in which an image is defined by a texture map comprising individual texture elements referred to as texels. In texture mapping procedures a texel is utilized to substitute or scale a surface property (e.g., diffuse color components, shading characteristics, dithering, etc.) at each pixel. Various trade-offs can be made in the selection or computation of a texel, trading off quality of results with computational complexity. For high quality results, bilinear interpolation between adjacent texels can be utilized, in which case up to 4 texels are required (i.e. a 2xc3x972 region of the texture image). For even higher quality results a technique called xe2x80x9cmipmappingxe2x80x9d can be used (along with trilinear interpolation) in which a 2xc3x972 region of texels is required from each of two adjacent levels of detail (LOD) (e.g., copies of a texture image reduced in size by 2{circumflex over ( )}N (for N=1,2, . . . )).
FIG. 2 is a conceptual example of a texture image configuration system 200. Texture image configuration system 200 includes 2 by 2 texel regions, such as texel region 291, set in 16 by 16 region tiles 270 through 285 arranged on an xe2x80x9cx axisxe2x80x9d 210, xe2x80x9cy axisxe2x80x9d 220 and xe2x80x9cz axisxe2x80x9d 230 coordinate system. The 2 by 2 texel regions can be arranged in any place within the texture images and can slide around, sometimes it may fall in a single tile, sometimes it may fall within two tiles and other times it may fall within four tiles. xe2x80x9cSlicesxe2x80x9d of a 3D image are defined by the xe2x80x9cz axisxe2x80x9d, for example texel region 291 is in slice 233 and texel region 292 is in slice 234.
In one example of a graphics system architecture a processor processes texel information retrieved from a cache memory component. The texture information is downloaded from a periphery memory component to the cache memory component in blocks of bits that define the texture information included in a particular tile. Usually an image is composed of numerous pixels and each pixel is modified by many texels represented by several bits. Thus a large amount of information or data needs to be processed and communicated in a typical computer graphics system. Electronic system design decisions on how to optimize the processing and communication of this information is usually affected by time dependencies and ordering constraints.
Thus, there is a great need for an architecture that provides time dependency and ordering constraint management in a reliable, cost effective, and extremely efficient manner. The architecture should be adaptable to a wide variety of electronic systems and have the ability to satisfy data processing and communication limitations of diverse components, including time dependency requirements and ordering constraints. For example, the architecture should facilitate utilization of parallel and sequential graphics processing and communication hardware in an effective and efficient manner to support retrieval of information for a cache memory.
The system and method of the present invention provides time dependency and ordering constraint management in a reliable, cost effective, and extremely efficient manner. The present invention is adaptable to a wide variety of electronic systems and has the ability to satisfy the data processing and communication requirements of diverse components, including time dependency requirements and ordering constraints. In one embodiment the system and method of the present invention ensures that the order of departing data substantially follows the order of arriving data while allowing efficient sharing and utilization of available hardware. For example, the present invention facilitates utilization of parallel and sequential graphics processing and communication hardware in an effective and efficient manner to support retrieval of information for a cache memory.
In one embodiment of the present invention, an electronic system and method maintains time dependencies associated with conversion of information between serial and parallel operations. A timing controller utilizes a tracking label (e.g., a representative bit) to track timing dependencies associated with the information and ensures the information is communicated and processed in an order that preserves the timing dependencies. The present invention tracks the order in which information is loaded in an electronic hardware component and ensures that the information loaded into the electronic hardware component at a particular time is processed without interruption by information loaded at a different time. For example, the timing controller tracks the order in which texel information associated with a pixel is parallelly loaded in a staging memory and causes the information loaded at a particular time to sequentially empty without interruption by information parallelly loaded in the staging memory at a different time.